The present invention relates to a memory addressing method and apparatus therefor, and more particularly, to a method of addressing a dynamic random access memory (DRAM) or a video random access memory (VRAM) for use in computer graphics application, and the apparatus therefor.
The DRAM should be provided with a refresh signal and thus requires a complex interfacing circuit therefor. However, since a DRAM can achieve four times the integration that a static random access memory (SRAM) can, DRAMs are widely adopted for use in the main memory of a computer system which requires a large capacity memory device. DRAM chips were originally introduced as a single-bit input/output method, but a four-bit input/output method was gradually instituted thereafter, which ultimately led to the TMS44C257 chip by Texas Instruments which is a dual four-bit input/output device.
FIG. 1 shows an internal configuration of a conventional DRAM with a dual four-bit input and output device. The conventional DRAM has a row address buffer 100 and column address buffer 110 for receiving and buffering a nine-bit external address signal ADD, a column decoder 120 for receiving and decoding the nine-bit column address signal YA.sub.8 to YA.sub.0 from the column address buffer 110 and thereby accessing column addresses, a first cell block 130 and second cell block 140, an input/output buffer 150 for buffering four-bit input and output signals of the first and second cell blocks 130 and 140 to selectively input and output the same in response to the most significant bit (MSB) signal XA.sub.8 of a nine-bit row address signal XA.sub.8 to XA.sub.0 supplied from the row address buffer 100, and a timing and control circuit 160 for receiving external timing and control signals /RAS, /CAS, /W and /G and generating internal timing and control signals. The first and second cell blocks each include two row decoders 132 and 142 for receiving an eight-bit row address signal XA.sub.7 to XA.sub.0 excluding the most significant bit XA.sub.8 from the row address buffer 100 and decoding the same, four 128K cell arrays 134 and 144 and four sense-amplifiers 136 and 146.
Referring to FIG. 2, the read operation of a conventional DRAM having the aforementioned configuration will now be described.
The external address signal A.sub.8 to A.sub.0 is buffered at the falling edge of the row address strobe signal /RAS by the row address buffer 100 and the buffered row address signal XA.sub.8 to XA.sub.0 is transmitted to row decoders 132 and 142 to then be decoded, thereby activating the decoded row (word) line of cell arrays 134 and 144. Subsequently, the external address signal A.sub.8 to A.sub.0 is buffered at the falling edge of the column address strobe signal /CAS by the column address buffer 110 and the buffered column address signal YA.sub.8 to YA.sub.0 is transmitted to column decoder 120 to then be decoded, thereby activating the decoded column (bit) line of cell arrays 134 and 144. Therefore, the cell being at the intersection of the activated row line and activated column line is accessed, and the data in the accessed cell is transmitted to input/output buffer 150 via sense-amplifiers 136 and 146. The input/output buffer 150 in response to MSB signal XA.sub.8 of the row address buffer 100 selectively outputs a four-bit output signal of the first and second cell blocks 130 and 140.
In such a read operation, since the row address signal and column address signal are supplied externally for every access operation to access the corresponding cells, the charge and discharge period ("a" of FIG. 2) of a row line becomes an invalid operation period, thereby increasing the access cycle. Therefore, when only column addresses are changed sequentially in an ascending series in the same row line, as shown in FIG. 3, by repeatedly activating the column address strobe signal /CAS during the activation state (low) of the row address strobe signal /RAS, the charge and discharge time of a row line is eliminated, thereby enabling a high-speed access operation which is known as a page mode. Specifically, the page mode is mainly used for repeatedly accessing sequential addresses, as in a VRAM.
However, the aforementioned page mode also requires a predetermined duration for the invalid period ("b" of FIG. 3) which extends from one column accessing to the next. For example, in sequentially reading the data from adjacent cells having addresses (0,0) and (0,1) in FIG. 1, a predetermined waiting interval is required after accessing address (0,0) and before accessing address (0,1) in order to prevent the data from colliding. This "wait" state is necessary since the column charged by column address "0" for accessing address (0,0) in the respective cell blocks 130 and 140 must be completely discharged and then the next column "1" must be charged so that address (0,1) may be accessed thereafter. That is, each column line needs a charge and discharge time.
Meanwhile, since the cell blocks 130 and 140 are simultaneously column-addressed by a single column decoder 120, four-bit output signals of the accessed cell blocks 130 and 140 reach input/output buffer 150 at the same time. Therefore, if the input/output buffer 150 outputs the four-bit output signal of the cell block 130, first, the four-bit output signal of the cell block 140 should wait, which results in increasing the accessing time by as much as the wait interval.
Also, since an external new column address signal should be input even for sequential addresses of an ascending series, for each accessing operation, external control is difficult to achieve.
In particular, in a dual port VRAM by which data is transmitted from the central processing unit through a random port and display data is transmitted to a cathode ray tube through a serial port, sequential addresses of an ascending series are repeated. Therefore, high-speed accessing and easy external control are required for obtaining high-resolution of cathode ray tubes.